Senior Physical Design Engineer

2 weeks ago


Sunnyvale, United States Chelsea Search Group, Inc. Full time
Senior Physical Design Engineer
Sunnyvale, CA (Onsite/Hybrid)
Start Date: November or December
Work Status: US Citizen only
Hourly Rate: $80-$90 on 1099 or C2C
6-12 months contract with possible extensions

The ideal candidates should be highly proficient in using all the Synopsys EDA tools/flows with little to no ramp-up time needed to make an immediate impact. You will be responsible for doing all aspects of SOC Physical Design implementation.


Required Qualifications:
  1. Experience: 10+ years
  2. Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS))
  3. Synopsys DC, DCG, DC TOPO
  4. Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by customer’s Physical Design Implementation team members
  5. Familiar with Synopsys Lynx a plus
  6. RTL Hand-over experience a plus for RTL to GDS
  7. Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning
  8. Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
  9. Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off
  10. Ability to define sign-off requirements/margins based on Foundry technology requirements a plus
  11. DFT experience with compression, scan, TDF, and MEMBIST a plus
  12. Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
  13. Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
  14. Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)
  15. Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR)
  16. Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus
  17. Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus
  18. Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out
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