TPU RTL Design Engineer — AI/ML SoC Acceleration
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Google is pursuing breakthroughs in AI/ML hardware acceleration. As a SoC Design Engineer, you’ll contribute to RTL design and verification for TPU architecture within data center accelerators, shaping how AI workloads are powered at scale.
You’ll collaborate across architecture, power, DV, and physical design teams to deliver robust chips and infrastructure. The role emphasizes cross-functional leadership, rigorous design practices, and interaction with software and system hardware