ASIC Verification Engineer
1 month ago
We are seeking an ASIC Verification Engineer.
Responsibilities:
- Write Functional and code coverage, digital design and verification of all areas of lifecycle
- Plan and debug tests
- h4 Development of test cases, checkers, and scoreboards
- Develop a complete test bench in System Verilog with Universal Verification Methodology (UVM)
- Work on simulators like Verilog Compiler Simulator (VCS)
- Plan for Assertion, Coverage metrics and coverage closure to make sure designs are verified thoroughly
- Digital Design and Verification (ASIC & RTL)
- Work on modem processors and protocols like AHB, AXI and perform design verification on all areas of verification lifecycle
Tools:
- UVM Methodology, Verilog, System Verilog
Requirements:
Minimum Education:
- Master's degree in Electronics / Electrical Engineering Technology
Minimum Experience:
- [Two (2) years] Two (2) years of experience must include two (2) years of experience in: UVM Methodology, Verilog, System Verilog.
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