Contract Hardware Engineer Mid.

3 weeks ago

San Jose, United States V R Della Infotech Inc Full time
Job DescriptionJob DescriptionDuties: Location: Mountain View, CA (Preferred) The client is open to considering remote if a candidate is strong. Note: This requisition is a reference to a Design Verification Engineer who comes with strong experience in SOC Verification, System Verilog, UVM, BFM/Driver/Monitor/Scoreboard component development, and AXI protocol. What candidate will Be Doing: At-least 8+ years of experience in System Verilog At-least 8+ year of experience in UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM Proficient in debug and assertions coding SOC Verification experience Proficient in AXI protocol Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively What we are looking for: At-least 8+ years of experience in System Verilog HVL. At-least 8+ year of experience in UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM Proficient in debug and assertions coding Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively

Skills: Location: Mountain View, CA (Preferred) The client is open to considering remote if a candidate is strong. Note: This requisition is a reference to a Design Verification Engineer who comes with strong experience in SOC Verification, System Verilog, UVM, BFM/Driver/Monitor/Scoreboard component development, and AXI protocol. What candidate will Be Doing: At-least 8+ years of experience in System Verilog At-least 8+ year of experience in UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM Proficient in debug and assertions coding SOC Verification experience Proficient in AXI protocol Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively What we are looking for: At-least 8+ years of experience in System Verilog HVL. At-least 8+ year of experience in UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. Proficient in SVTB/UVM Proficient in debug and assertions coding Verification closure with team Make/Perl/Python Ensure customer satisfaction. Reporting to customer on daily or weekly progress effectively

Education: Bachelor's Degree

Required Skills: SIMULATIONS,TEST PLAN,VERILOG,DEBUG,CODING,
Additional Skills: SOC,PERL,PYTHON,

Minimum Degree Required: Bachelor's Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak, Read, Write )
Department: Cost of goods sold : 1100
Job Category: IT

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