Hybrid Lead Front-End Verification Engineer, RISC-V
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Tenstorrent in Austin or Santa Clara is seeking a Design Verification Engineer to contribute to unit-level verification of our RISC-V CPU front end. You will build testbenches, generate stimulus, and develop checkers for complex microarchitectural scenarios.
You should be fluent with SystemVerilog, UVM, and C++, and comfortable collaborating with RTL designers to trace and fix fetch bugs. This role is hybrid and offers a wide exposure to cutting-edge hardware and software integration.
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