Principal or Senior Principal Circuit Design Engineer
11 hours ago
Requisition ID: R10167447
Category: Engineering
Location: Linthicum, Maryland, United States of America | Annapolis Junction, Maryland, United States of America
Clearance Type: Polygraph
Telecommute: No- Teleworking not available for this position
Shift: 1st Shift (United States of America)
Travel Required: Yes, 10% of the Time
Relocation Assistance: Relocation assistance may be available
Positions Available: 1
The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions (APS) Business is seeking a Principal or Senior Principal Circuit Design Engineer / Layout Engineer. The ideal candidate will have a solid understanding of microelectronic electrical principles, demonstrated organizational skills, and a willingness to learn and grow in a team environment.
Responsibilities (including, but not limited to):
Create custom designs and layouts that could include Process Control Monitor (PCM) structures, reticle alignment marks, and physical measurement structures.
Provide floor planning guidance and support.
Create chip designs in various technologies for process prove-in, experimentation, and test support.
Perform both frontend and backend verification of designs.
Participate in reticle composition and tape out activities.
Document work performed.
Basic Qualifications for a Principal Circuit Design Engineer / Layout Design Engineer:
Bachelor’s Degree in a STEM related field with 5 years of related experience; 3 years with Masters; 0 years with PhD.
Excellent verbal, written, and interpersonal communication skills.
Navigate file structures in the LINUX environment.
US Citizen with ability to obtain and maintain a TS/SCI with polygraph security clearance.
Basic Qualifications for a Senior Principal Circuit Design Engineer / Layout Design Engineer:
Bachelor’s Degree in a STEM related field with 9 years of related experience; 7 years with Masters; 4 with a PhD.
Excellent verbal, written, and interpersonal communication skills.
Navigate file structures in the LINUX environment.
US Citizen with ability to obtain and maintain a TS/SCI with polygraph security clearance.
This position requires onsite support at our Linthicum, MD or Annapolis Junction, MD campuses.
Preferred Qualifications:
Understanding of the Semiconductor fabrication process and process development.
Understanding of Process Design Kit (PDK) Development.
Skilled in the use of the Cadence Virtuoso capture tool.
Proficient in the use of Cadence ASSURA or Siemens Mentor Calibre DRC/LVS verification tools.
Experience in Superconducting Reciprocal Quantum Logic circuit design practices.
Current Secret/TS SCI clearance.
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