Principal Digital Engineer
2 weeks ago
As a Principal Logic Design Engineer, the candidate will be reporting to the Technical Director, Engineering and is a Full-Time position.
Responsibilities
- Design of high-speed CMOS Digital Logic which includes the following responsibilities:
- Planning:
- lead digital designer roles
- project managing
- design block specification
- system-level simulation
- documentation
- Implementation
- RTL design in Verilog
- lint
- clock domain crossing (CDC) analysis
- top level integration
- synthesis
- timing analysis
- timing closure
- DFT-related tasks
- Verification:
- work with verification team on planning and execution
- simulation
- debugging block and system level simulations
- formal verification
- preparation of technical reviews and product/block documentation
- Flow and methodology
Qualifications
- Bachelor's or Master's Degree in Electrical or Computer Engineering
- 7+ years of relevant digital/ASIC/IC design experience
- Significant Experience with RTL coding in Verilog and/or VHDL
- Significant Experience with standard ASIC software tools (synthesis, simulation, equivalence checking, static timing analysis)
- Strong knowledge of scripting, Linux/Unix environment, and basic C/C++ programming
- Thorough understanding of ASIC design flow
- Successful past digital leadership roles
- Strong design and system knowledge
- Design for verification experience or understanding (assertion based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
- Self-starter and fast learner with excellent interpersonal skills
- Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
- Additional knowledge of Analog blocks for behavior modelling and DDR protocols, experience with memory controller, PCIe digital controller, and/or embedded MCU subsystem designs is a plus
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