Senior RTL Design Engineer

2 weeks ago


San Jose, United States ZealTech, Inc. Full time

RTL Design Engineer - Senior

Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in Computer Engineering

KEY RESPONSIBILITIES:
Perform RTL design of digital components in Verilog/systemverilog.
Analyze/fix Lint and CDC errors of the components.
Guarantee quality/timely deliverables meeting project s schedule.
Help to improve/automate design process.

PREFERRED EXPERIENCE:
Knowledge of RISK-V processor integration Express
Multi-clock domain designs.
Design constraints for synthesis and static timing analysis.
Knowledge of AXI/AMBA protocol
Knowledge of front-end RTL design tools and methodologies.
Knowledge of scripting languageslikePerl, tcl or cshell

Please mention years of experience beside each skill Below:

  • RTL design
  • Verilog
  • systemverilog
  • Lint
  • CDC errors
  • RISK V
  • AXI
  • AMBA protocol

Submission form:

Full name

Phone

Email

Are you ok for onsite at Sanjose ?

Work authorization:

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