Mixed Signal Design Engineer, SerDes, PLL, DDR PHY
6 days ago
Mixed Signal Design Engineer - SerDes, PLL, DDR PHY
As a member of the mixed signal team, the candidate's work encompassing the development of the state of the art mixed signal IP for SOC including SerDes, PLL, DDR PHY, MIPI PHY, etc. The candidate will have exposure to a broad range of IP design phases, including analog circuit level transistor design, IP top level mixed-mode modeling, digital system RTL design, verification, synthesis, STA analysis, simulation and verification in mixed-signal IC environment. Work with different teams to ensure the IP delivery and bring up.
Qualifications:
Either digital oriented professional and or analog oriented professional experience is required.
For Digital oriented:
• Good knowledge of digital front-end design, including Verilog coding and timing analysis.
• Familiar with analog integrated circuit and mixed signal verification.
• Knowledge of digital back-end flow is a plus.
For Analog oriented:
• Experience and or knowledge of the analog integrated circuit and mixed signal design and verification.
• Familiar with digital front-end design, including Verilog coding and timing analysis is a plus.
General:
- 1 -3 years of experience.
- Knowledge on signal integrity is a plus.
- MS or PH.D. in electrical engineering.
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