ASIC Clock Design Engineer
2 weeks ago
Company
Quest Global
Job Area
Hardware Engineering
Job Description Summary
General Summary:
ASIC Clock Design Engineer
Join the Quest Global as a Senior ASIC Clock Engineer for the most cutting-edge work. Quest Global assists its customers in developing their next generation flagship product lines (mobile devices, complex routers/switches, consumer products, storage, microprocessor, graphics
processors etc.). This includes developing cutting edge technologies that are key and rare in the industry. We offer a fun, creative and flexible work environment.
As a Senior ASIC Clock Design Engineer, you will work with different teams like microarchitecture, SOC, GPU, CPU, Defence teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.
Title :: Senior ASIC Clock Design Engineer
Location :: Palo Alto, California
Expection from Engineer ::
- A successful candidate should have 4 to 10 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.
- Full Chip Clock Architecture analysis, Design, and Implementation.
- Scripting in TCL/Python or other similar languages. Debug/decode existing scripts.
- Well versed with Constraints, STA and good knowledge of Primetime (PT).
PREFERRED EXPERIENCE:
- Expertise in Full Chip Clocking or Sub-system level implementation.
- Experience in TCL/Python and other languages needed.
- Should be strong in scripting and decode/debug old existing scripts.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer/Electronics/Electrical Engineering
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