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Analog Layout Design Engineer
6 days ago
Job Description:
- 7+ years’ experience required.
- Mastery of layout and verification tools and methodologies.
- Experience in Cadence layout (Virtuoso, VXL) and Calibre verification (ERC, DRS, LVS) preferred
- Strong communication, debugging and analytical skills with complex technical concepts
- Experience with advanced deep sub-micron CMOS, especially FinFET technologies preferred
- Comprehensive understanding of the target process to balance layout and design needs, e.g. crosstalk, RC delay, electro-migration, IR drop, self-heating, shielding, matching, guard rings and latch up
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Analog Layout Design Engineer
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