Senior PMIC Engineer

4 weeks ago

Austin, United States Acceler8 Talent Full time

The role necessitates a minimum of 8 years of involvement in power management design.


Acceler8 is in search of a seasoned professional to devise on-chip power provision solutions for high-capacity processors. Your responsibilities will encompass delineating and crafting the CPU power supply framework. This entails drafting the schematic layout of DC-DC power converters or LDOs, conducting analyses on supply reliability and effectiveness, and projecting enhancements in system performance.


You'll collaborate with specialized layout and physical design engineers to actualize the design and conduct post-layout validations. Moreover, this position mandates furnishing a PI signoff model and closely liaising with PI engineers to fulfill the on-chip IR-drop signoff requisites.


Additionally, you'll contribute to packaging designs, a pivotal aspect of the comprehensive CPU power strategy. If you possess a robust engineering background coupled with a fervor for groundbreaking advancements, we invite you to apply. This role offers an exceptional opportunity to contribute to state-of-the-art CPU design and power enhancement initiatives.


Job Requirement:


- Proficient in power management circuit designs, encompassing buck and boost regulators, along with Low Dropout Regulators (LDOs) for mobile systems.

- Demonstrated expertise in steering top-tier analog custom layout.

- Thorough grasp of analog IC flow and proficiency with CAD tools such as Cadence Virtuoso and Matlab.

- Familiarity with mixed-signal simulation within the Cadence AMS environment.

- Sound comprehension of CPU DVFS design and scenarios involving low power consumption.

- Adept at understanding die-package-board power delivery network co-design constraints and associated trade-offs.

- Background in AMS simulation and validation methodologies.

- Proficiency in programming or scripting languages for data analysis and workflow automation.

- Competency in analog circuit behavior modeling using Verilog-AMS or Verilog-A.

- Minimum of 8 years of practical experience in power management circuit designs.

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