Design Verification Engineer

1 month ago


San Francisco, California, United States OPTnation Full time
Skills and Qualification Required
  • Minimum Qualification o BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience .
o 3+ years of UVM experience (so this implies 3+ years of SystemVerilog as well).o Deep understanding of coverage constrained-random transaction level .o Experience with Verdi/VCS is a musto Experience with test plan documentationo Familiarity with Python3/Bash/Tcl scripting is a musto Experience with debugging simulation failures to guide digital design.

Experience with fixed point arithmeticPreferred Qualifications -o BSEE/MSEE/BSCompE/MSCompE with 10 years of industry experience .o Experience with performance analysis and performance characterization a plus.o Experience with using Hierarchical Verification Plan is a plus.o Experienced with a full ASIC/SOC tapeout from beginning to end.o Experience with video processing or graphics pipelines is a plus.o Experience with floating point arithmetic in addition to fixed point arithmetic.o Mininum 5-20 yrs.



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