Design Verification Engineer

3 weeks ago


San Jose, United States Insight Global Full time

Role: Verification Engineer (FPGA Design Focus)

Type: Long Term Contract

Start Date: ASAP

Pay: $60-80/hr



Overview:

We are looking for an experienced Verification Engineer with a focus on FPGA design to join our growing team in San Jose. The ideal candidate will have a strong background in Verilog, UVM (Universal Verification Methodology), and experience with digital design, lab skills, and debugging. You will work on current Cisco routers, contributing to the development of new chassis and design work. This is a critical role for immediate large-scale projects, where design verification quality has been a key challenge.


Key Responsibilities:


• Develop and modify System Verilog test cases for digital design verification.

• Perform FPGA design tasks, including Verilog coding, simulations, and lab debugging.

• Collaborate with the design team on-site 5 days a week, ensuring smooth execution of verification plans.

• Work closely with networking technologies (e.g., Cisco) and participate in verification efforts.

• Coordinate with engineers to meet project deadlines for chassis and route design.

• Provide expertise in verification for FPGA and design environments, addressing challenges in finding qualified talent.


Requirements:

• 10+ years of experience in FPGA design, Verilog, and verification processes.

• Strong background in UVM and simulation methodologies.

• Proven experience with digital design, lab skills, and debugging in FPGA environments.

• Ability to work on-site in San Jose 5 days a week and collaborate effectively within a team.

• Experience in networking systems (e.g., Cisco) is a plus.


Opportunities:

• Join a growing team working on large-scale current router projects.

• Engage in cutting-edge FPGA design and verification tasks in a hands-on lab environment.

• Collaborate with top engineers in the field and contribute to the development of the next generation of networking systems.



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