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Senior RTL Design Engineer

2 months ago

Boston, United States Acceler8 Talent Full time

Senior RTL Design Engineer


Acceler8 Talent is seeking a Senior RTL Design Engineer to join a very well-funded AI hardware startup that’s developing groundbreaking hardware to solve critical bottlenecks in next-gen computing workloads.


Founded by a group of architects, developers, and hackers who are responsible for building silicon infrastructure and systems technology that powers more than half of today's worldwide data center traffic, this company is thoroughly equipped to revolutionize networking in the age of Gen AI. In addition to having a super team of founders, they are exceedingly well-funded, having a $50 million A round, followed by a B round of $125 million, with investments from Sutter Hill Ventures and Nvidia.


Responsibilities

  • Own the entire logic and block design from analysis of design approach and tradeoffs, to specification, through RTL implementation.
  • Deliver a robust, high performance design that meets the timing, area, reliability, testability, and power requirements set by an ambitious cross-functional engineering team.
  • Collaborate with system software, architecture, and microarchitecture experts on the functional and performance requirements to develop high-throughput engineers for processing and storing data.
  • Support functional verification and performance validation to ensure the product meets the performance demands of advanced data centers.
  • Support silicon bringup and post-silicon testing of mission critical functions.


Skills/Qualifications

  • B.S Electrical/Computer Engineering with 7+ years industry experience or M.S Electrical/Computer Engineering with 5+ years of industry experience
  • Successful track record in designing and building one or more of the following: high-performance Network Interface Controllers, Smart-NICs, or DPUs processing multithreaded data paths and ordering capabilities.
  • Expertise designing blocks such as DMA controllers, and queuing/doorbell engines.
  • Proven industry experience designing high-performance packet buffering subsystems, demonstrating knowledge of traffic management concepts.
  • Expertise with SystemVerilog, and strong understanding of Python, Perl, or similar scripting and programming languages


This position will be hybrid-remote, with 3 days on-site per week from their Boston office.


They are looking to get someone started ASAP and will offer compensation consisting of competitive base salary + stock options.


Please apply here or contact jtyler@acceler8talent.com if you’d like to learn more.