Design Verification Engineer
3 months ago
This startup in Mountain View, CA is on a mission to become THE computing platform for GenAI. Founded by one of the leads on the development of Google’s Palm Large Language model and one of the leads on Google’s first ML accelerator. They are building hardware by combining deep domain experience for large language models, graphics processing units and other machine-learning models, enabling developers and programmers to make artificial intelligence better, faster and cheaper.
They are looking for a principal-level Design Verification Engineer to join their team as they create best-in-class silicon for high-performance and sustainable GenAI.
This is a full-time hybrid role (Tues-Thurs) in the Mountain View, CA office.
Job Responsibilities
- Enhance their verification methodology by developing scalable solutions for blocks, subsystems, full-chip, and system-level validation
- Take ownership of specific portions of verification execution at the subsystem and chip levels, including the creation of testbenches, tests, and related artifacts to ensure both structural and functional coverage closure.
- Lead planning and conduct intermediate and sign-off reviews of verification test plans, monitor execution progress, and achieve verification closure for various silicon milestones such as design freeze and tapeout.
Job Requirements
- Proven experience driving verification from an architecture and/or design specification through to production silicon.
- Proficiency in SystemVerilog, Python, C/C++, Bluespec, and similar scripting and programming languages used for verification and silicon modeling.
- Hands-on experience with advanced verification methodologies such as UVM and assertion-based verification (ABV); a strong familiarity with both formal and simulated verification techniques is essential.
- Demonstrated experience in creating portable tests and drivers for verification, applicable to silicon validation and post-silicon debug.
- Deep understanding of silicon micro-architecture and design concepts, particularly in high-performance computing (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related functionalities.
- Familiarity with emulation and prototyping platforms and methodologies is advantageous.
- Practical experience in silicon debug and bring-up processes is a plus.
All candidates must be authorized to work in the United States and work from their offices in Mountain View Tuesdays-Thursdays.
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