Sr Systems Verification Engineer

Description Robotics & Digital Surgery, part of the Johnson & Johnson family of companies, is recruiting for a Systems Verification Engineer , located in Santa Clara, CA. At Johnson & Johnson,we believe health is everything. Our strength in healthcare innovation empowers us to build aworld where complex diseases are prevented, treated, and...

Job Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller Significant UVM SystemVerilog experience in complex test-benches Experience working with DRAM controller PHYs memory models is preferred Significant experience with general verification flows and metrics Excellent debug...

Job Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller• Significant UVM SystemVerilog experience in complex test-benches• Experience working with DRAM controller PHYs memory models is preferred• Significant experience with general verification flows...

Role/Responsibilities: You will work closely with the design team to define strategy and requirements for block-level and chip-level testing infrastructure. With a thorough understanding of design intent, you will drive the verification environment and the creation of test plans for unit-level and chip-level verification, implement test benches and test...

Role/Responsibilities: You will work closely with the design team to define strategy and requirements for block-level and chip-level testing infrastructure. With a thorough understanding of design intent, you will drive the verification environment and the creation of test plans for unit-level and chip-level verification, implement test benches and test...

Role/Responsibilities: You will work closely with the design team to define strategy and requirements for block-level and chip-level testing infrastructure. With a thorough understanding of design intent, you will drive the verification environment and the creation of test plans for unit-level and chip-level verification, implement test benches and test...

Job Description Our client, a world leader in Pharmaceuticals & In vitro diagnostics (IVD), is looking for a "Sr System Engineer Job Type: Long-term Contract (Possibility Of Further Extension)Location: Santa-Clara, CA Company Benefits include Healthcare (Medical, Dental, & Vision) Paid Sick leave 401k (with 2% employer match) RSPONSIBILITIES Develop and...

Senior Design Verification Engineer Santa Clara CA Experience Level: 7-15 years. JOB DESCRIPTION 1 Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. Good knowledge of EDA tools. Experience with signal...

Senior Design Verification Engineer Santa Clara CA Experience Level: 7-15 years. JOB DESCRIPTION 1 Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. Good knowledge of EDA tools. Experience with signal...

Senior Design Verification Engineer Santa Clara CA Please make an application promptly if you are a good match for this role due to high levels of interest. Experience Level: 7-15 years. JOB DESCRIPTION 1 Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or...

Senior Design Verification EngineerSanta Clara CAExperience Level: 7-15 years. JOB DESCRIPTION 1Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills.Good knowledge of EDA tools. Experience with signal...

Senior Design Verification EngineerSanta Clara CAExperience Level: 7-15 years. JOB DESCRIPTION 1Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills.Good knowledge of EDA tools. Experience with signal...

Job DescriptionJob DescriptionSenior Systems EngineerLocation: Santa Clara, CA 95054 - Fully OnsiteDuration: 6 Month Contract to HireThe IT organization is looking for a Sr. IT engineer. You will be responsible for research, design, deploy, and maintain Email services, Windows Servers, Active Directory, VDI, and email related services. Once service deployed,...

Qualcomm's Power Management Systems team leads the industry in the system architecture and verification of high-performance Power Management Integrated Circuits (PMICs) and Power Management Units (PMUs) embedded in our chipsets for smartphones/tablets, notebooks, automotive infotainment and ADAS system, a variety of cutting-edge consumer electronics...

Qualcomm's Power Management Systems team leads the industry in the system architecture and verification of high-performance Power Management Integrated Circuits (PMICs) and Power Management Units (PMUs) embedded in our chipsets for smartphones/tablets, notebooks, automotive infotainment and ADAS system, a variety of cutting-edge consumer electronics...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Job Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where they are. Develop test plans and test benches for module level verification ...