Layout Engineer

2 days ago

Rolling Meadows, United States Acro Service Corp Full time

Basic Qualifications:

• Ability to obtain a Security Clearance from the U.S. Department of Defense.

• Principal: Minimum of an associate’s degree in a relevant field with 8 years of relevant experience or 5 years with a Bachelor’s Degree in a relevant field.

• Sr. Principal: Minimum of associate’s degree in a relevant field with 12 years of relevant experience or 9 years with a bachelor’s degree in a relevant field.

• Experience laying out custom analog/custom digital/custom RF cells as a top level lead.

• Proficient in floor planning especially top-down, area optimization, and handling critical devices and signals with the proper care.

• Demonstrated expertise creating a floorplan of a complete IC to minimize parasitic issues related to layout and packaging.

• Demonstrated expertise developing high quality layouts for complex Analog and Mixed Signal (“AMS”) designs using Cadence Virtuoso XL/GXL.

• Considerable experience using Cadence Layout XL (a power user) to do full custom layout of complete mixed signal ICs and/or test structures.

• Solid debugging skills of results generated by industry standard layout verification tools.

• Demonstrated expertise isolating critical analog blocks from noisy sources through layout noise-coupling suppression techniques.

• Solid knowledge of how to address EM/IR issues, prevent latch-up, mitigate ESD, and ensure component and signal path matching.

• High attention to detail and ability to deliver verified and optimized layout quickly.

• Ability to distinguish between devices and nets in a schematic that need to be handled with care vs. those that do not.

• Strong interpersonal and team skills for cross-functional collaboration and the ability to work independently.

Advantageous Qualifications:

• Knowledge of semiconductor device physics, process development, analog/mixed signal integrated circuit design, manufacturing, and testing,

• Experience using SKILL, Perl, C-Shell, and/or Python to increase layout productivity.

• Experience using Cadence Virtuoso's other advanced features (GXL, EAD, and Constraint Manager).

• Experience in deep submicron CMOS circuits with finFETs and dual patterning.

• Technical understanding of IR drop, RC delay, electro-migration, self-heating, and coupling capacitance.

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