Design Verification Engineer
7 days ago
A RISC-V Start Up is seeking SOC Verification - Emulation engineers to work on projects ranging from subsystem level to multi-chip level, covering all aspects of emulation including functional, performance, microarchitecture, and debugging.
Role Overview
As an SOC Verification - Emulation Engineer, you will develop Emulation and FPGA-based prototyping systems to support our SOC projects. You will collaborate with architecture, design, verification, and software/firmware teams to develop emulation models and capabilities for various use cases such as functional verification, performance testing, software/firmware bring-up, running realistic workloads, power estimation, hybrid-simulation, and post-silicon debugging. Your responsibilities may include developing and debugging emulation flows, designing testbenches, monitors or transactors, synthesizing RTL for emulation, and creating RTL collateral for emulation.
Key Responsibilities
- Create and support emulation models from RTL and drive SOC bring-up on emulation platforms.
- Debug test failures and resolve simulation/emulation mismatches.
- Develop compile and runtime flows for various emulation use cases including functional verification, hybrid simulation, post-silicon debugging, power estimation, and software/firmware enablement.
- Develop capabilities to run tests on emulators and assist in bring-up processes from RTL prototyping through post-silicon validation.
- Collaborate with tool vendors to drive requirements and resolve tool issues.
- Contribute to methodology and automation improvements to enhance emulation efficiency and value.
Requirements
- Deep understanding of digital logic design, CPU/SOC architecture, microarchitecture, and industry-standard interfaces and memory subsystems.
- Proficient in Verilog/SystemVerilog.
- Proficient in C/C++.
- Familiarity with verification methodologies and tools such as simulators, waveform viewers, and build/run automation.
- Experience with emulation tools such as Palladium, Zebu, Veloce, Protium, or HAPS.
- Experience with QEmu or other software simulators is a plus.
- Experience in simulation acceleration using transactors or vendor-provided accelerated verification IP is a plus.
- Skilled in performance analysis and debugging techniques.
- Proficiency in scripting languages such as Python or TCL is a plus.
- Excellent problem-solving skills, strong written and verbal communication skills, excellent organizational skills, and high self-motivation.
- Ability to work effectively in a team and be productive under aggressive schedules.
Education and Experience
- PhD, Masters Degree, or Bachelors Degree in a technical subject area.
- Apply now to be a part of a dynamic team driving the future of SOC emulation technology
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