Senior RFIC Layout Engineer
4 weeks ago
Kyocera International, Inc. is seeking a highly skilled Senior RFIC Layout Engineer to join our team. As a key member of our design team, you will be responsible for providing technical guidance and leadership to a team of layout engineers.
The ideal candidate will have extensive industry experience in custom RF/analog layout for RF transceivers, with a strong knowledge of deep sub-micron CMOS and SOI processes. You will be responsible for performing detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, phase shifters, bias, and power management and integration digital IPs.
You will also be responsible for taking ownership of the chip's top-level integration, ensuring seamless integration of various RF and analog blocks, meeting performance and power targets, and resolving any layout-related challenges. Additionally, you will lead and coordinate the tapeout process, collaborating with cross-functional teams, such as design, verification, packaging, manufacturing and foundry to ensure a successful and timely tapeout of the chip.
The successful candidate will have a deep understanding of advanced RFIC layout techniques and methodologies, and will drive the development of best practices for efficient and reliable layout design. You will also be responsible for overseeing the DRC, LVS and DFM checks to ensure compliance with design specifications and foundry rules, and will work closely with design engineers to resolve any layout-related issues.
Requirements:
- Bachelor's degree in Electrical Engineering or related field, with at least 10+ years of relevant industry experience.
- Extensive industry experience in custom RF/analog layout for RF transceivers with a strong knowledge of deep sub-micron CMOS and SOI processes.
- Demonstrated ability to lead and mentor a team of layout engineers effectively.
- Strong communication and interpersonal skills to collaborate with cross-functional teams.
- Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Mentor Calibre,...) and familiarity with layout design flows for advanced technology nodes.
- Strong analytical and problem-solving skills to identify and address layout-related issues efficiently.
Pay rate range: $170,000 - $275,000
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