Hardware Design-for-Test Engineer

3 days ago


San Jose, California, United States Cisco Systems, Inc. Full time

Cisco Systems, Inc. is seeking an experienced Hardware Design-for-Test (DFT) Engineer to join our Silicon One development organization in San Jose, CA.

Estimated salary for this position: $140,000 - $170,000 per year based on industry standards.

About the Job

As an ASIC DFT Engineer at Cisco Systems, Inc., you will be responsible for implementing hardware design-for-test features that support Automatic Test Equipment (ATE), in-system test, debug, and diagnostics needs of the designs.

You will work closely with Front-end RTL teams and Backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. Your team will participate in creating innovative hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die, driving reusable test and debug strategies.

Responsibilities
  • Implementing hardware design-for-test features that support ATE, in-system test, debug, and diagnostics needs of the designs.
  • Developing innovative DFT IP in collaboration with multi-functional teams and playing a key role in full-chip design integration with testability features coordinated in the RTL.
  • Working closely with design/design-verification and PD teams to enable the integration and validation of test logic in all phases of the implementation and post-silicon validation flows.
Requirements
  • Bachelor's or Master's degree in Electrical or Computer Engineering required with at least 10 years of good experience in latest innovative trends in DFT, test, and silicon engineering.
  • Good experience with JTAG protocols, Scan and BIST architectures, including memory BIST and boundary scan.
  • Good experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
  • Verification skills include System Verilog Logic Equivalency checking and validating the Test-timing of the design.
  • Experience working with Gate level simulation, debugging with VCS and other simulators.
  • Post-silicon validation and debug experience; ability to work with ATE patterns, P1687.
  • Strong verbal skills and ability to thrive in a multifaceted environment.
  • Scripting skills: Tcl, Python/Perl.
PREFERRED SKILLS
  • Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification.
  • DFT CAD development - Test Architecture, Methodology, and Infrastructure.
  • Test Static Timing Analysis.
  • Post-silicon validation using DFT patterns.


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