Senior Design Verification Engineer for Ethernet Projects

4 days ago


Burlingame, California, United States CV Library Full time
Job Title:

Senior Design Verification Engineer for Ethernet Projects

About CV Library

We are a leading job portal that connects talented professionals with exciting career opportunities.

Job Description

We are seeking an experienced Senior Design Verification Engineer to join our team. As a Senior Design Verification Engineer, you will play a key role in ensuring the quality and reliability of our products.

Key Responsibilities
  • Develop and execute test plans to verify the functionality of Ethernet projects.
  • Write and maintain high-quality test cases and scenarios to ensure thorough testing.
  • Collaborate with cross-functional teams to identify and resolve defects.
  • Update existing testbench components to improve efficiency and effectiveness.
  • Debugging failing tests in regression suites.
Requirements
  1. Minimum 5 years of experience as a Design Verification Engineer with a proven track record of success.
  2. Hands-on experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).
  3. Familiarity with Synopsys VCS/Verdi or Cadence Incisive tools.
  4. Experience with UPF-based simulation flows.
  5. Strong programming skills in C/C++.
  6. Proficiency in Tcl and Python scripting.
Preferred Qualifications
  1. Experience with Power and Performance FPGA validation.
  2. Knowledge of Power Aware GLS flow.
  3. Background in ASIC design.
  4. Formal property verification expertise.
  5. Experience with complex SoCs.
  6. Coverage merging across simulation and formal.
What We Offer

We offer a competitive salary of $150,000 - $180,000 per year, depending on experience, as well as a comprehensive benefits package.



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