Senior Design Verification Engineer for Ethernet Projects
4 days ago
Senior Design Verification Engineer for Ethernet Projects
About CV LibraryWe are a leading job portal that connects talented professionals with exciting career opportunities.
Job DescriptionWe are seeking an experienced Senior Design Verification Engineer to join our team. As a Senior Design Verification Engineer, you will play a key role in ensuring the quality and reliability of our products.
Key Responsibilities- Develop and execute test plans to verify the functionality of Ethernet projects.
- Write and maintain high-quality test cases and scenarios to ensure thorough testing.
- Collaborate with cross-functional teams to identify and resolve defects.
- Update existing testbench components to improve efficiency and effectiveness.
- Debugging failing tests in regression suites.
- Minimum 5 years of experience as a Design Verification Engineer with a proven track record of success.
- Hands-on experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).
- Familiarity with Synopsys VCS/Verdi or Cadence Incisive tools.
- Experience with UPF-based simulation flows.
- Strong programming skills in C/C++.
- Proficiency in Tcl and Python scripting.
- Experience with Power and Performance FPGA validation.
- Knowledge of Power Aware GLS flow.
- Background in ASIC design.
- Formal property verification expertise.
- Experience with complex SoCs.
- Coverage merging across simulation and formal.
We offer a competitive salary of $150,000 - $180,000 per year, depending on experience, as well as a comprehensive benefits package.
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