Senior Principal Engineer, Cache Coherency Subsystem Verification

4 days ago

Austin, Texas, United States Ampere Full time
About the Role

We are seeking a highly skilled Senior Principal Engineer to lead the verification of our server-class microprocessor-based Coherent Mesh interconnect subsystem. As a key member of our Design Verification team, you will be responsible for ensuring the functional correctness and performance of our CPUs.

Key Responsibilities
  • Strategize and execute cache coherency subsystem verification efforts across verification platforms
  • Review architecture and microarchitecture specs and influence design/microarchitecture decisions
  • Define verification strategy and test plans for cache coherency subsystem verification
  • Architect and lead development of verification collateral including test benches, random test generators and checkers
  • Lead and contribute to day-to-day execution of all verification activities to meet tape out quality requirements
  • Define post-si validation plans and debug post-silicon system level failures
  • Mentor/guide the work of other engineers to achieve project goals
About You

We are looking for a highly experienced engineer with a strong background in IP and subsystem design verification. The ideal candidate will have a solid understanding of high-performance multi-core processor architecture and microarchitecture, especially OOO memory and cache coherency protocols.

  • Minimum MS & 8 years or BS & 12 years of IP and subsystem design verification experience
  • Solid understanding of high-performance multi-core processor architecture and microarchitecture, especially OOO memory and cache coherency protocols
  • Prior experience in verifying Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols or other high performance interconnect protocols
  • Experienced in building new verification test benches using industry standard languages like System Verilog, UVM/OVM
  • Programming experience in 1 or more languages common to the industry (e.g., C, C++)
  • Experience in automating design/verification tasks using perl/python or other scripting languages
  • Knowledge of ARM or x86 memory architecture and assembly language programming
  • Prior experience in leading design verification efforts and strong verification mindset with excellent attention to detail
  • Technical leadership skills like ability to articulate vision, inspire the team, plan, and organize team's work, make difficult decisions
  • Strong analytical and problem skills and able to communicate technical concepts, status, and issues clearly
About Ampere

Ampere is a semiconductor design company that is leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future.

We offer a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits. The full base pay range for this role is between $129,000 and $215,000, except in the San Francisco Bay Area where the range is between $143,000 and $238,000. We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company.

We are an inclusive and equal opportunity employer and welcome applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

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