Senior Lead DFT Design Engineer
4 weeks ago
Cadence US is seeking a highly skilled Senior Lead DFT Design Engineer to join our team. As a key member of our digital design team, you will be responsible for leading the design for test (DFT) architecture and implementation for our SoC/ASIC products.
Key Responsibilities:
- Lead DFT architecture and implementation for SoC/ASIC products
- Develop and maintain DFT insertion flows and tools
- Collaborate with cross-functional teams to ensure DFT requirements are met
- Provide technical guidance and support to junior engineers
- Stay up-to-date with industry trends and emerging technologies
Requirements:
- 15-20 years of professional experience in SoC/ASIC digital design with focus on DFT
- Strong knowledge of DFT insertion flows and tools
- Experience with compression scan insertion, LBIST, and other scan technologies
- Intimate knowledge of memory built-in self-test (MBIST)
- Expertise in automatic test pattern generation (ATPG) to achieve design test coverage goals
- Debug and analysis of failures to improve fault coverage
- Verification of ATPG testbenches and debugging root cause of simulation mis-compares
- Working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687
- Ability to work in a collaborative team environment
- Prior experience with Cadence tools and flows is highly desirable
About Cadence US:
Cadence US is a leading provider of electronic design automation (EDA) software and services. We are committed to helping our customers design and deliver innovative products that shape the world of technology.
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