Silicon Verification Engineer V

1 week ago


Mountain View, United States CV Library Full time

Job Title: Silicon Verification Engineer V

Job Location: Remote

Job Duration: 2 Months on W2 (with high chances of extension)

Summary:

The main function of Silicon Verification Engineer is to be a part of the test-plan process, creating, testing, and implementing various verification plans.

Job Responsibilities:

Define, document, and implement a UVM verification environment including agents and scoreboards

Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral

Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes

Support post-silicon verification activities of the products working with design and product teams

Typical Day in the Role

Purpose of the Team: The purpose of this team is referred to as SCIPS, is to work on digital IP intellectual property and acceleration, including DMA (Direct Memory Access) functions and data compression, decompression, encryption, and decryption. Their digital IPs are integrated into 's SoC chip used in Azure Data Centers.

Key projects: This role will contribute to Accelerator IP.

Typical task breakdown and operating rhythm: The role will consist of 85% Development, 15% Meetings.

Compelling Story & Candidate Value Proposition

What makes this role interesting? - This role provides the opportunity to Delivering IP to s Azure /AI siliconx.

Unique Selling Points

Skills:

1. Proficient in using Verilog and VMM/OVM/UVM

2. Experience in pre and post silicon verification test flow and automated test benches

3. Effective communication, collaboration, and teamwork skills

Education/Experience:

Bachelor s degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required

10+ years of relevant experience required.

Top 3 Hard Skills Required + Years of Experience

1. Minimum 5+ years experience with UVM.

2. Minimum 5+ years experience with System Verilog.

3. Minimum 5+ years experience with Test Bench development.



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