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Senior Analog/Mixed Signal Design Verification Engineer
4 months ago
Silergy Corp, one of the fastest growing analog and mixed-signal semiconductor companies, was founded in Sunnyvale, California by a group of technology innovators and business leaders from Silicon Valley with an average 30 years’ experience. We design and produce innovative mixed-signal and analog ICs that utilize our industry-leading process technologies. Widely used in industrial, automotive, consumer, computing and communication devices, our products are designed to improve efficiency and to conserve or measure energy use. We are committed to providing industry-leading performance at an affordable solution cost. Our recent customer success in multiple market segments is driving the need for rapid expansion of skills and resources in the US.
Key Responsibilities
Building DV methodologies, test-plan development, verification environment development
Develop verification plans including stimulus and checkers, verification coverage using a variety of compliance metrics
Work with the design and verification team to develop reusable UVM verification platform
Run regression simulations, debug, and to meet verification coverage goals
Work with digital design engineers for RTL design and debug
Work with analog design engineers for real number behavior models integration
Documenting bugs tracking and resolve system
Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
Qualifications
BS degree in technical discipline (EE or CS) with minimum 3 years of relevant experience
Minimum of 3 years DV experience
Verification flow with UVM, SystemVerilog, and Verilog
Analog Mixed Signal (AMS) verification with Real Number Modeling
Experienced with the full verification life cycle
Developing scalable and portable test-benches
Proven experience with verification methodologies
Familiar with DV tools such as simulators, waveform viewers. Able to build and run automation test benches, develops asserts & checkers to meet coverage, run gate level simulations
UVM knowledge, C/C++ level knowledge
Knowledge of one of the scripting languages such as Python, Perl, TCL
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