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Senior ASIC Design Engineer

4 months ago

San Jose, United States USA Tech Recruitment Full time

Senior ASIC Design Engineer - GenAI

Are you interested in joining one of the fastest growing GenAI start ups in the world? The company have recently secured a huge amount of funding and are looking to expand their HW teams in the USA. This role would allow working from their offices in San Jose.

Position: Senior ASIC Design Engineer

Role Overview: Lead the microarchitecture and design implementation of a high-performance, low-power convolutional neural network accelerator ASIC.

Responsibilities:

  • Author micro-architecture specs and review test plans.
  • Architect and implement complex RTL designs.
  • Integrate CPU and 3rd-party IPs into the SoC.
  • Collaborate with physical design team on implementation and timing.
  • Analyze code coverage and assist verification team.
  • Perform post-silicon validation and software bring-up in the lab.

Qualifications:

  • 5+ years of ASIC design experience with Verilog/System Verilog.
  • Experience in IP integration, especially CPU IP into SoC.
  • Knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, and multicore CPU operation.
  • Familiarity with AMBA/APB/AXI protocols and processor interfaces (SPI, eMMC, GPIO, I2C).
  • Proficiency in front-end tools and low power design (UPF).
  • Experience with timing closure at high frequencies is a plus.
  • Interest in AI architectures for convolution and transformer workloads.
  • B.S. (M.S. preferred) in Electrical/Computer Engineering.
  • Self-starter motivated to work in a dynamic startup environment.

If you are interested please do apply or send a copy of your CV to me at ccanneaux@eu-recruit.com