Sr. Staff Timing

2 weeks ago

Austin, United States Samsung Electronics Co., Ltd. Full time
Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us

Role and Responsibilities

As a Sr. Staff Timing (STA) Engineer, you will be responsible for ensuring the timing integrity of SARC/ACL premium GPU IPs. It is a highly visible role and requires collaboration with cross-functional design teams, EDA-partners and intra-functional teams. The role requires a strong technical contributor with proficient skills in developing and implementing timing analysis and convergent strategies in cutting-edge technology.

  • You deliver hands on responsibility in top level timing constraints generation/debug on complex GPU IPs
  • You have proven STA timing leadership credentials in top level clocking and timing constraints and closure (functional and Test)
  • You understand different implementation styles of clock in design and how these affect latency and skew
  • You utilize your in-depth understanding of timing sign off flow and methodology including timing budgeting, derating and timing across different voltage domains
  • You interact with RTL and SOC physical implementation teams to resolve timing issues pertaining to block and SOC signoff closure
  • You mentor junior engineers in different areas of timing flows and methodologies
  • You're able to influence flow and methodology enhancements for improvement
  • You work independently and lead/influence cross functional teams to make good technical design trade-offs between power, area, timing
Skills and Qualifications
  • 15+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 13+ years of experience with a Master's Degree, or 11+ years of experience with a PhD
  • Solid background in the ASIC design flow with many years of successful design tape outs
  • Experience with 5nm finfet or smaller process nodes is strongly preferred
  • Working knowledge and detail understanding of POCV is required
  • Strong hands-on experience with industry standard STA tools (PrimeTime, Tempus) is required
  • Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools an added plus
  • Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs
  • Strong working knowledge of formal equivalency checks, LP checks, timing constraints, UPF.
  • Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage
  • Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred
  • Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail
  • Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must


Our Team

We're building a team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Physical Design group is part of the larger Design Implementation team at SARC/ACL. We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow.

Our Xclipse GPU is the first mobile GPU with ray tracing technology that enables console-level graphic for Samsung Galaxy smartphones. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Total Rewards

At Samsung - SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,557 and $270,563. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

#SARC #Hybrid

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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