ASIC Design Engineer

2 weeks ago

San Jose, United States Advanced Micro Devices, Inc. Full time

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

ASIC DESIGN ENGINEER

THE ROLE:

A senior technical contributor that drives end-to-end delivery of SerDes solution directly contributing to, and coordinating implementation and optimization across multiple teams. The position will involve interfacing with software and hardware engineering teams and AMD partners to plan, develop and optimize use cases. This is an exciting opportunity to work on the cutting edge of SerDes Technology.

THE PERSON:

You are a subject matter expert and strong technical contributor with SerDes/PHY experience. You excel as part of a team where communication and team skills are highly valued.

KEY RESPONSIBILITIES:

  • Write microarchitecture and/or design specifications
  • Design, implement, and debug complex logic designs
  • Integrate complex IPs into the SOC
  • Work with other specialists that are members of the SOC Design - Verification, Emulation, STA, and Physical Design teams
  • Support all front end integration activities (Lint, CDC, Synthesis, and ECO)
  • Implement design automation via Python or other languages
  • Collaborate with software and systems teams to ensure a high quality system

PREFERRED EXPERIENCE:

  • Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
  • Writing specifications and converting them to design
  • Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable
  • Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks.
  • Experience in low-power design techniques such as clock- and power-gating is a plus
  • Ability to communicate effectively across all internal groups
  • Familiarity with scripting languages like Perl or Python or Tcl is a plus
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) is a plus
  • Familiarity with security concepts is a plus
  • Familiarity with software and operating concepts is a plus
  • Excellent communication and collaboration skills

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in related discipline preferred

LOCATION:

San Jose, CA

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