Senior ASIC Design Engineer

1 week ago


Redwood City, United States Vorticity Inc Full time
The Role
  • Design and develop high-performance, synthesizable RTL code using SystemVerilog, Verilog or VHDL
  • Participate in microarchitecture definition and refinement
  • Implement and optimize logic for specific functionalities and performance targets
  • Conduct functional verification through simulations and formal methods
  • Collaborate with architects, verification engineers, and physical designers to ensure successful integration and production
  • Write clear and concise technical documentation
  • Stay up-to-date with the latest advancements in digital design technologies and methodologies
Skills & Qualifications:
  • Bachelor's or Master’s degree in Computer Science, Electrical Engineering, or a related field
  • Minimum 2+ years of experience (will consider bright individuals even with lower experience) in RTL design and verification
  • Proven expertise in SystemVerilog, Verilog or VHDL
  • Strong understanding of computer architecture
  • Familiarity with synthesis and timing constraints
  • Knowledge of programming languages: Python, C, C++. Tcl, shell scripting, CUDA C++ are a plus.
  • Excellent written and verbal communication skills
  • Strong ability to work independently and as part of a team
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