ASIC Engineering Technical Leader

2 days ago

San Jose, United States Cisco Systems, Inc. Full time

The application window is expected to close on 12/30/2024

This is an onsite role and will require working out of the Milpitas/San Jose office location

Who We Are

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

What You'll Do

The Core Hardware Business Unit is looking for a motivated Senior Verification engineer/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.

  • Architect block, cluster and top level DV environment infrastructure
  • Create DV infrastructure from scratch for block, cluster and top level environments
  • Maintaining existing DV environments and enhancing them
  • Ensuring complete verification coverage through implementation and review of code and functional coverage
  • Working closely with designers
  • Supporting tests done with emulation
  • Work closely with software teams and debug issues found during firmware development

Minimum Qualifications:

  • 10+ years ASIC design verification experience with a Bachelor’s or Master’s degree
  • Prior experience with ASIC verification using UVM/System Verilog.
  • Prior experience in verifying complex blocks, clusters and top level for SoC
  • Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
  • Prior experience with cross-functional teams, and possess the drive to learn and grow
  • Prior experience on one or more protocols – PCIe, Ethernet, RDMA, TCP

Preferred Qualifications:

  • Lead a team of engineers to complete verification of a complex block, cluster or chip-level design
  • Lead verification for a complete SOC or ASIC
  • Prior Experience with Forwarding logic/Parsers/P4
  • Formal verification (iev/vc formal) knowledge

We Are Cisco

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.

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