SoC Architect

2 weeks ago


San Jose, United States Capgemini Full time

Responsibilities:

  1. You will be the primary point of contact with customers from a technical perspective.
  2. Responsible for SoC Architecture but you will not be involved with the day-to-day details of the design.
  3. Develop architecture and micro-architecture from specs (Full chip design for multimillion gates SoC).
  4. Manage IP dependencies, planning and tracking of all front-end design related tasks.
  5. Drive project milestones across the design, verification, and physical implementations.
  6. Manage interface with Value Chain Aggregator partners for manufacturing and testing.
  7. Manage design from architecture to tape-out, foundry and outside semiconductor assembly & test (OSAT).
  8. Responsible for determining the types of internal resources required for projects.
Required Qualifications:
  1. Strong understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, top level test plans, and verification.
  2. 15+ years’ experience with SoC design (Digital design and development RTL).
  3. Experience with chiplet architecture and partitioning for SiP packages.
  4. Experience with various bus protocols AHB, AXI and peripherals like USB, SDCC.
  5. Previous experience with Synopsys Design Compiler Synthesis and formal verification with Cadence LEC but you will not be utilizing these tools directly.
  6. Experience making effective and timely decisions, even with incomplete information.
  7. Leadership skills to provide mentoring, and direction to small to medium sized groups.
  8. Strong communication skills to effectively work with internal and external program stakeholders.
Desired Qualifications:
  1. Understanding of Memory controller designs and Microprocessors is an added advantage.
  2. Understanding of Chip IO design and packaging are an added advantage.
  3. Experience with high performance, low power, or automotive functional safety expertise at advanced process nodes.
  4. PMP Certification.
Location:

Must reside in San Jose CA (Bay Area).

Technical environment:

ARM, DDR, Synopsys/Cadence Tools, Python/TCL, SystemVerilog.

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