SoC Architect
2 weeks ago
Responsibilities:
- You will be the primary point of contact with customers from a technical perspective.
- Responsible for SoC Architecture but you will not be involved with the day-to-day details of the design.
- Develop architecture and micro-architecture from specs (Full chip design for multimillion gates SoC).
- Manage IP dependencies, planning and tracking of all front-end design related tasks.
- Drive project milestones across the design, verification, and physical implementations.
- Manage interface with Value Chain Aggregator partners for manufacturing and testing.
- Manage design from architecture to tape-out, foundry and outside semiconductor assembly & test (OSAT).
- Responsible for determining the types of internal resources required for projects.
- Strong understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, top level test plans, and verification.
- 15+ years’ experience with SoC design (Digital design and development RTL).
- Experience with chiplet architecture and partitioning for SiP packages.
- Experience with various bus protocols AHB, AXI and peripherals like USB, SDCC.
- Previous experience with Synopsys Design Compiler Synthesis and formal verification with Cadence LEC but you will not be utilizing these tools directly.
- Experience making effective and timely decisions, even with incomplete information.
- Leadership skills to provide mentoring, and direction to small to medium sized groups.
- Strong communication skills to effectively work with internal and external program stakeholders.
- Understanding of Memory controller designs and Microprocessors is an added advantage.
- Understanding of Chip IO design and packaging are an added advantage.
- Experience with high performance, low power, or automotive functional safety expertise at advanced process nodes.
- PMP Certification.
Must reside in San Jose CA (Bay Area).
Technical environment:ARM, DDR, Synopsys/Cadence Tools, Python/TCL, SystemVerilog.
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