PCIe SOC RTL Design Lead

ASIC Design Verification Engineer (PCIe/CXL Switch SoCs)San Jose, CAFull-time + BenefitsUS Citizen or US Permanent ResidentResponsibilities:Test bench development using SystemVerilog and UVMTest plan and test case developmentExperience in developing SV Functional coverage models and SVA assertions and cover propertiesRegression setup and debug RTL level and...

Sr. Digital Design Engineer - PCIe / DDR / NVMWe are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of...

Sr. Digital Design Engineer - PCIe / DDR / NVMWe are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of...

Sr. Digital Design Engineer - PCIe / DDR / NVMWe are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of...

Position Summary:Needed domains are NVMe and PCIe and desired experience having been involved in SSD controller design. The tasks are:1 Debugging issues seen in the lab if they appear to be hardware related and the firmware team needs help. Debugging activities include but are not limited to: 1 Analyzing the logs, examining registers, capturing PCIe traces,...

The RTL design engineer will need strong RTL coding experience with ASIC frontend design flow experience including microarchitecture, lint check, CDC/RDC run/fixGood debugging skills as a block owner10+ years of RTL experience is preferableAny PCIe experience would be a big plus, but not a must-have requirement.

The RTL design engineer will need strong RTL coding experience with ASIC frontend design flow experience including microarchitecture, lint check, CDC/RDC run/fixGood debugging skills as a block owner10+ years of RTL experience is preferableAny PCIe experience would be a big plus, but not a must-have requirement.

The RTL design engineer will need strong RTL coding experience with ASIC frontend design flow experience including microarchitecture, lint check, CDC/RDC run/fixGood debugging skills as a block owner10+ years of RTL experience is preferableAny PCIe experience would be a big plus, but not a must-have requirement.

Position Summary:Needed domains are NVMe and PCIe and desired experience having been involved in SSD controller design. The tasks are:1 Debugging issues seen in the lab if they appear to be hardware related and the firmware team needs help. Debugging activities include but are not limited to: 1 Analyzing the logs, examining registers, capturing PCIe traces,...

Position Summary:Needed domains are NVMe and PCIe and desired experience having been involved in SSD controller design. The tasks are:1 Debugging issues seen in the lab if they appear to be hardware related and the firmware team needs help. Debugging activities include but are not limited to: 1 Analyzing the logs, examining registers, capturing PCIe traces,...

Position Summary:Needed domains are NVMe and PCIe and desired experience having been involved in SSD controller design. The tasks are:1 Debugging issues seen in the lab if they appear to be hardware related and the firmware team needs help. Debugging activities include but are not limited to: 1 Analyzing the logs, examining registers, capturing PCIe traces,...

Lead RTL Design Engineer / RISC-VWe are seeking an experienced design engineer to lead development of complex IP subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills.Responsibilities:Lead microarchitecture and RTL design of complex IP subsystems partnering...

Wireless SOC Design Verification Engineer As part of our team, you will have the opportunity to verify a set of complex SOCs. Our team integrates multiple sophisticated IP-level DV environments, crafts highly reusable best-in-class UVM Testbenches, implements effective coverage-driven and directed test cases, deploys new tools, and implements methodologies...

Position Overview At Samsung, we are looking for a highly skilled GPU Top RTL Integration Lead to join our growing team at the Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL). As a key member of our GPU RTL team, you will be responsible for leading various aspects of GPU Top RTL/Design and Integration. ...

RTL Design Engineer Looking for a solid RTL Design Engineer who has a strong background in supporting RISC-V houses. The primary technology will be focused around SOCs that are built around ML Accelerators. This person should have a solid background in RTL Design and also have an understanding of verification flows. This person should be a strong engineer...

Job OverviewWe are seeking a highly skilled Senior ASIC Design Engineer to join our team at Cisco Silicon One. As part of this role, you will be responsible for designing and developing complex high-performance ASICs used in Cisco's networking products and third-party custom-built hardware solutions.About the RoleThis is a senior-level position that requires...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, Low Power, Power Characterization. Lead technical campaigns and strategies...

Position Summary:We are seeking a highly skilled Design Verification Engineer with experience in domains such as PCIe and DDR. The ideal candidate will have a background in working with companies that develop SOC. This position requires working on-site for one of our clients in San Jose, California.Responsibilities:Develop and execute verification plans for...

Position Summary:We are seeking a highly skilled Design Verification Engineer with experience in domains such as PCIe and DDR. The ideal candidate will have a background in working with companies that develop SOC. This position requires working on-site for one of our clients in San Jose, California.Responsibilities:Develop and execute verification plans for...

Position Summary:We are seeking a highly skilled Design Verification Engineer with experience in domains such as PCIe and DDR. The ideal candidate will have a background in working with companies that develop SOC. This position requires working on-site for one of our clients in San Jose, California.Responsibilities:Develop and execute verification plans for...