Hardware Engineering
2 days ago
Job Description: Remote role. Preference will be given to candidates in PST.
Max bill rate of Hourly.
Minimum Qualifications:
- 5+ years of experience as a DV engineer
- Bachelor degree in Electrical/Computer Engineering or Computer Science
Top Non-Negotiable Skill Sets Required:
- Power and performance modeling or DV (C, system C, system Verilog, or MATLAB)
- Strong DV background (test plan development, test writing, UVM)
- Experience with low power verification (UPF)
- Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows
Duties:
- Responsible for low power verification including both dynamic and static verification
- Write and augment existing test plans
- Implement testbench and scoreboards/checkers
- Implement test sequences as per plan and debug failures
- Achieve 100% functional, code, and power coverage
- Work closely with designers, micro architects & f/w to resolve issues
- Ability to communicate & articulate clearly progress/issues with project leads
Skills:
Must Have:
- 5+ years of proven experience as a DV engineer
- Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
- Hands on experience with Synopsys VCS/Verdi or Cadence Incisive tools
- Experience with UPF based simulation flow
- 2+ years of experience with C/C++
Wish List/Nice to Have:
- Power and performance FPGA validation
- Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, Python
- Experience with Power Aware GLS flow
- Tcl and Python (or similar) scripting
- ASIC design experience
- Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
- Experience with complex SoCs
- Knowledge of coverage merging across simulation and formal
- MSEE/CS or equivalent experience
Education:
- Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
- Master's Degree (not required)
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